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MDT10C55B
1. General Description
This ROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power Power-on Reset Power edge-detector Reset Sleep Mode for power saving 5 types of oscillator can be selected by programming option: INTRCInternal 4 MHz RC oscillator RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator
consump-tion and high noise immunity. On chip memory inclu-des 1K words of ROM, and 72 bytes of static RAM.
2. Features
The followings are some of the features on the hardware and software : Fully CMOS static design 8-bit data bus On chip ROM size : 1K words Internal RAM size : 72 bytes 36 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.5 V ~ 5.5 V Operating frequency : 0 ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction Addressing modes include direct, indirect and relative addressing modes
HFXTHigh frequency crystal oscillator 3 oscillator start-up time can be selected by programming option: 20 ms, 40 ms, 80 ms 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler On-chip RC oscillator based Watchdog Timer(WDT) Wake-up from sleep on pin change
3. Applications
The application areas of this MDT10C55B range from appliance motor control and high speed automotive to low power remote transmitters/receivers, small instruments, chargers, toy, automobile and PC pe-ripheral ... etc.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 1
2006/12
Ver. 1.0
MDT10C55B
4. Pin Assignment
MDT10C55B1P/MDT10C55B1S MDT10C55B3P/MDT10C55B3S
VDD 1 PB5 PB4 PB3 PC5/RTCC PC4 PC3 2 3 4 5 6 7
14 VSS 13 12 11 10 9 8 PB0 PB1 PB2 PC0 PC1 PC2
VDD PB5 PB4 /MCLR PC5/RTCC PC4 PC3 VDD OSC1 OSC2/PB4 /MCLR PC5/RTCC PC4 PC3
1 2 3 4 5 6 7 1 2 3 4 5 6 7
14 13 12 11 10 9 8 14 13 12 11 10 9 8
VSS PB0 PB1 PB2 PC0 PC1 PC2 VSS PB0 PB1 PB2 PC0 PC1 PC2
MDT10C55B2P/MDT10C55B2S
MDT10C55B4P/MDT10C55B4S
VDD 1 OSC1 OSC2/PB4 PB3 PC5/RTCC PC4 PC3 2 3 4 5 6 7
14 VSS 12 12 11 10 9 8 PB0 PB1 PB2 PC0 PC1 PC2
5. Pin Function Description
Pin Name PB5~0 PC4~0 PC5/RTCC /MCLR OSC1 OSC2 Vdd Vss I/O I/O I/O I/O I I O Function Description Port B, TTL input level, PB3 input only. Port C, TTL input level. Real Time Clock/Counter, Schmitt Trigger input levels. Master Clear, Schmitt Trigger input levels. Oscillator Input Oscillator Output Power supply Ground
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 2
2006/12
Ver. 1.0
MDT10C55B
6. Memory Map
(A) Register Map Address 00 01 02 03 04 06 07 08~1F 30~3F 50~5F 70~7F (1) IAR (Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter register) : R1 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 JUMP --- from instruction word RTWI, RET --- from STACK General purpose registers Description Indirect Addressing Register RTCC PC STATUS MSR Port B Port C
A9
A8 Write PC, JUMP, CALL --- from STATUS b5 RTWI, RET --- from STACK
A7~A0
Write PC --- from ALU JUMP, CALL --- from instruction word RTWI, RET --- from STACK
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 3
2006/12
Ver. 1.0
MDT10C55B
(4) STATUS (Status register) : R3 Bit 0 1 2 3 4 5 6 7 Symbol C HC Z PF TF PAGE ---- PCWUF Carry bit Half Carry bit Zero bit Power down bit WDT Timer overflow Flag bit ROM page select bit Unimplemented Pin change wake up from sleep Function
(5) MSR (Memory Bank Select Register) : R4 b7 b6 b5 b4 b3 b2 b1 b0
Read only "1"
BANK Select Indirect Addressing Mode
(6) PORT B : R6 PB5~PB0, I/O register, PB3 input only. (7) PORT C: R7 PC5~PC0, I/O register. (8) TMR (Time Mode Register) Bit Symbol Function Prescaler Value RTCC rate 000 1:2 001 1:4 010 1:8 011 1 : 16 100 1 : 32 101 1 : 64 110 1 : 128 111 1 : 256 Prescaler assignment bit : 0: RTCC 1: Watchdog Timer RTCC signal Edge : 0: Increment on low-to-high transition on RTCC pin 1: Increment on high-to-low transition on RTCC pin RTCC signal set : 0: Internal instruction cycle clock 1: Transition on RTCC pin PortB pull-high :(RB0,RB1,RB3,RB4) 0: Enable 1: Disable WDT rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
2--0
PS2--0
3
PSC
4
TCE
5
TCS
6
PBPHB
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 4
2006/12
Ver. 1.0
MDT10C55B
Bit 7 Symbol PBWUB Function PortB wake-up : (RB0,RB1,RB3,RB4) 0: Enable 1: Disable
(9) CPIO B, CPIO C (Control Port I/O Mode Register) The CPIO register is "write-only" "0", I/O pin in output mode; "1", I/O pin in input mode. (B) Program Memory Address 000-3FF 000 Program memory The starting address of power on, external reset or WDT time-out reset. Description
8. Reset Condition for all Registers
Register CPIO B CPIO C TMR IAR RTCC PC STATUS MSR PORT B PORT C Address 00h 01h 02h 03h 04h 06h 07h Power-On Reset --11 1111 --11 1111 1111 1111 xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx 110x xxxx --xx xxxx --xx xxxx /MCLR Reset --111 1111 --11 1111 1111 1111 uuuu uuuu uuuu uuuu 0000 0000 #00# #uuu 11uu uuuu --uu uuuu --uu uuuu WDT Reset --11 1111 --11 1111 --11 1111 uuuu uuuu uuuu uuuu 0000 0000 #00# #uuu 11uu uuuu --uu uuuu --uu uuuu
Note : uunchanged, xunknown, - unimplemented, read as "0" #value depends on the condition of the following table
Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Wake-up from SLEEP on pin change
Status: bit 7 0 0 0 0 1
Status: bit 4 u 1 0 0 1
Status: bit 3 u 0 1 0 0
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 5
2006/12
Ver. 1.0
MDT10C55B
9. Instruction Set :
Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO R STWR R LDR R, t LDWI I SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t DECRSZ R, t ANDWR R, t ANDWI i IORWR R, t IORWI i XORWR R, t XORWI i COMR R, t RRR RLR CLRW CLRR BCR BSR R R, b R, b R, t R, t No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register Increment register, skip if zero Add W and register Subtract W from register Decrement register Decrement register, skip if zero AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Function Operating None 0WT 0WT, stop OSC WTMODE StackPC WCPIO r WR Rt IW [R(0~3) R(4~7)] t R + 1t R + 1t W + Rt R Wt or (R+/W+1t) R 1t R 1t R Wt i WW R Wt i WW R Wt i WW /Rt R(n) R(n-1), CR(7), R(0)C R(n)r(n+1), CR(0), R(7)C 0W 0R 0R(b) 1R(b) Skip if R(b)=0 Skip if R(b)=1 TF, PF TF, PF None None None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z C C Z Z None None None None Status
BTSC R, b BTSS R, b
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 6
2006/12
Ver. 1.0
MDT10C55B
Instruction Code 1000nn nnnnnnnn 1010nn nnnnnnnn 110000 nnnnnnnn 110001 iiiiiiii 11001n nnnnnnnn Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive `' Exclusive `' Logic AND `' b t : : 0 1 R : C : HC : Z : / : x : i : n : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address Mnemonic Operands LCALL n LJUMP n CALL RTWI JUMP n i n Function Long CALL subroutine Long JUMP to address Call subroutine Return, place immediate to W JUMP to address Operating nPC, PC+1Stack nPC nPC, PC+1Stack StackPC,iW nPC Status None None None None None
10. Oscillator start up timer condition
Oscillator Type INTRC,RC HF,XT,LF Porwer-on reset 20ms,40ms,80ms 20ms,40ms,80ms Subsequest resets 300us 20ms,40ms,80ms
11. Electrical Characteristics
*Note: Temperature=25C 1.Operation Current : (1) HF (C=10p) , WDT - enable 4M 2.5V 3.0V 4.0V 5.0V 5.5V 250uA 350uA 500uA 800uA 1.2mA 10M 600uA 750uA 900uA 1.3mA 1.8mA 20M 1.2mA 1.4mA 1.8mA 2mA 3mA Sleep 3uA 8uA 16uA 30uA 50uA
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 7
2006/12
Ver. 1.0
MDT10C55B
(2) XT (C=10p) , WDT - disable 1M 2.5V 3.0V 4.0V 5.0V 5.5V 100uA 120uA 230uA 480uA 820uA 4M 200uA 280uA 550uA 840uA 1.2mA 10M 500uA 710uA 1.2mA 1.7mA 2.2mA Sleep 1uA 1uA 1uA 1uA 1uA
These parameters are for reference only.
(3) RC , WDT - Enable , @Vdd = 5.0V C R 4.7k 10k 3p 47k 100k 300k 470k 4.7k 10k 20p 47k 100k 300k 470k 4.7k 10k 100p 47k 100k 300k 470k 4.7k 10k 300p 47k 100k 300k 470k Freq. 8.7M 4.3M 1M 513K 175K 107K 5M 2.5M 580K 370K 93K 58K 1.9M 940K 210K 135K 34K 21K 786K 389K 85K 55K 14K 9K Current 2.4mA 1.3mA 370uA 260uA 190uA 180uA 1.9mA 1.1mA 320uA 240uA 190uA 180uA 1.4mA 770uA 280uA 220uA 190uA 180uA 1.3mA 680uA 250uA 210uA 180uA 170uA
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 8
2006/12
Ver. 1.0
MDT10C55B
(4) LF (C=10p) , WDT - enable 32K(50p) 455K(50p) 2.5V 3.0V 4.0V 5.0V 5.5V 20uA 30uA 50uA 100uA 200uA X 70uA 130uA 200uA 300uA 1M 60uA 90uA 160uA 240uA 330uA Sleep 3uA 8uA 16uA 30uA 50uA
These parameters are for reference only.
(5) INT_RC , WDT - disable 4MHz 3.0V 4.0V 500uA 800uA Sleep 1uA 1uA
5.0V 1mA 1uA These parameters are for reference only.
2. Input Voltage (Vdd = 5V) : Port Vil TTL Schmitt trigger Vih TTL Schmitt trigger These parameters are for reference only. Min Vss Vss 2V 3.2V Max 1.5V 1.0V Vdd Vdd
3. Output Voltage (Vdd = 5V) : PA,PB Voh Vol Voh Vol 3.3V 0.8V 4.3V 0.6V Condition Ioh =-20mA Iol =+20mA Ioh = -5mA Iol = +5mA
These parameters are for reference only.
4. Output Current (Max.) (Vdd = 5V) : Port B: Source current Sink current These parameters are for reference only. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw Current 25mA 25mA
P. 9
2006/12
Ver. 1.0
MDT10C55B
Port C: Source current Sink current These parameters are for reference only. Current 25mA 25mA
5. The basic WDT time-out cycle time : Time 2.5V 3.0V 4.0V 5.0V 25ms 23ms 20ms 19ms
5.5V 18ms These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 10
2006/12
Ver. 1.0

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